80C652 Datasheet, PDF (15/25 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
AC ELECTRICAL CHARACTERISTICS – I²C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
SCL TIMING CHARACTERISTICS
t_HD;STA
START condition hold time
t_LOW
SCL LOW time
t_HIGH
SCL HIGH time
t_RC
SCL rise time
t_FC
SCL fall time
SDA TIMING CHARACTERISTICS
≥ 14 t_CLCL
≥ 16 t_CLCL
≥ 14 t_CLCL
≤ 1µs
≤ 0.3µs
> 4.0µs¹
> 4.7µs¹
> 4.0µs¹
–²
< 0.3µs³
t_SU;DAT1
Data set-up time
≥ 250ns
> 20 t_CLCL – t_RD
t_SU;DAT2 SDA set-up time (before rep. START cond.)
≥ 250ns
> 1µs¹
t_SU;DAT3 SDA set-up time (before STOP cond.)
≥ 250ns
> 8 t_CLCL
t_HD;DAT
Data hold time
≥ 0ns
> 8 t_CLCL – t_FC
t_SU;STA
Repeated START set-up time
≥ 14 t_CLCL
> 4.7µs¹
t_SU;STO
STOP condition set-up time
≥ 14 t_CLCL
> 4.0µs¹
t_BUF
Bus free time
≥ 14 t_CLCL
> 4.7µs¹
t_RD
SDA rise time
≤ 1µs
–²
t_FD
SDA fall time
≤ 0.3µs
< 0.3µs³
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t_CLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. t_CLCL = 1/f_OSC = one oscillator clock period at pin XTAL1. For 63ns (42ns) < t_CLCL < 285ns (16MHz (24MHz) > f_OSC > 3.5MHz) the SI01
interface meets the I²C-bus specification for bit-rates up to 100 kbit/s.
TIMING SIO1 (I²C) INTERFACE
START or repeated START condition
t_RD
SDA
(INPUT/OUTPUT)
t_FD
t_RC
t_FC
SCL
(INPUT/OUTPUT)
t_HD;STA t_LOW
t_HIGH
t_SU;DAT1
t_HD;DAT
repeated START condition
STOP condition
t_SU;STA
START condition
t_BUF
t_{SU; STO}
0.7 V_DD
0.3 V_DD
t_SU;DAT3
t_SU;DAT2
0.7 V_DD
0.3 V_DD
1996 Aug 15
15