80C652 Datasheet, PDF (14/25 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
AC ELECTRICAL CHARACTERISTICS^{1, 2} (24 MHz type)
24MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
1/t_CLCL
2
t_LHLL
2
t_AVLL
2
t_LLAX
2
t_LLIV
2
t_LLPL
2
t_PLPH
2
t_PLIV
2
t_PXIX
2
t_PXIZ
2
t_AVIV
2
t_PLAZ
2
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
1.2
24
43
2t_CLCL–40
17
t_CLCL–25
17
t_CLCL–25
102
4t_CLCL–65
17
t_CLCL–25
80
3t_CLCL–45
65
3t_CLCL–60
0
0
17
t_CLCL–25
128
5t_CLCL–80
10
10
t_RLRH
3, 4
RD pulse width
150
6t_CLCL–100
t_WLWH
3, 4
WR pulse width
150
6t_CLCL–100
t_RLDV
3, 4
RD low to valid data in
118
t_RHDX
3, 4
Data hold after RD
0
0
t_RHDZ
3, 4
Data float after RD
55
t_LLDV
3, 4
ALE low to valid data in
180
t_AVDV
3, 4
Address to valid data in
210
t_LLWL
3, 4
ALE low to RD or WR low
75
175
3t_CLCL–50
t_AVWL
3, 4
Address valid to WR low or RD low
92
4t_CLCL–75
t_QVWX
3, 4
Data valid to WR transition
12
t_CLCL–30
t_DW
3, 4
Data setup time before WR
162
7t_CLCL–130
t_WHQX
3, 4
Data hold after WR
17
t_CLCL–25
t_RLAZ
3, 4
RD low to address float
0
t_WHLH
3, 4
RD or WR high to ALE high
17
67
t_CLCL–25
Shift Register
t_XLXL
t_QVXH
t_XHQX
t_XHDX
t_XHDV
5
Serial port clock cycle time³
5
Output data setup to clock rising edge³
5
Output data hold after clock rising edge³
5
Input data hold after clock rising edge³
5
Clock rising edge to input data valid³
0.5
12t_CLCL
283
10t_CLCL–133
23
2t_CLCL–60
0
0
283
External Clock
t_CHCX
t_CLCX
t_CLCH
t_CHCL
6
High time³
6
Low time³
6
Rise time³
6
Fall time³
17
17
17
17
5
5
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
5t_CLCL–90
2t_CLCL–28
8t_CLCL–150
9t_CLCL–165
3t_CLCL+50
0
t_CLCL+25
10t_CLCL–133
t_{CLCL –} t_CLCX
t_{CLCL –} t_CHCX
5
5
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
1996 Aug 15
14