80C652 Datasheet, PDF (12/25 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 9 through 11 for I_DD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 5ns;
V_IL = V_SS + 0.5V; V_IH = V_DD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V_DD. See Figure 9.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 5ns; V_IL = V_SS + 0.5V;
V_IH = V_DD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V_DD; EA = RST = V_SS. See Figure 10.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V_DD;
EA = RST = V_SS. See Figure 11.
5. 2V ≤ V_PD ≤ V_DDmax.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I²C specification, so an input voltage below 0.3V_DD will be recognized as a
logic 0 while an input voltage above 0.7V_DD will be recognized as a logic 1.
7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2V.
8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
9. Under steady state (non-transient) conditions, I_OL must be externally limited as follows: Maximum I_OL = 10mA per port pin; Maximum
I_OL = 26mA total for Port 0; Maximum I_OL = 15mA total for Ports 1, 2, and 3; Maximum I_OL = 71mA total for all output pins. If I_OL exceeds the
test conditions, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
10. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0.9V_DD specification when the
address bits are stabilizing.
11. I_DDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I_DDMAX is given in mA.
40
I_DD
(mA)
30
20
50
I_DD
(mA)
40
30
(1)
(1)
20
10
10
(2)
(2)
0
0
4
8
12
16
f_XTAL1 (MHz)
(1) MAXIMUM OPERATING MODE: V_DD = V_DDmax
(2) MAXIMUM IDLE MODE: V_DD = V_DDmax
These values are valid within the specified
frequency range.
0
0
4
8
12
(1) MAXIMUM OPERATING MODE: V_DD = V_DDmax
(2) MAXIMUM IDLE MODE: V_DD = V_DDmax
These values are valid within the specified
frequency range.
16
24
f_XTAL1 (MHz)
Figure 1. I_DD vs. Frequency
1996 Aug 15
12