PCF5083 Datasheet, PDF (119/136 Pages) NXP Semiconductors – GSM signal processing IC

Philips Semiconductors
GSM signal processing IC
Objective specification
PCF5083
NO
PARAMETER
MIN.
RF Device Control Bus timing - Mode 2 (see Fig.33; note 12)
1
RFEN1 to RFEN4 setup time to RFCLK HIGH
−
2
RFEN1 to RFEN4 hold time after RFCLK LOW
−
3
RFCLK LOW time
−
4
RFCLK HIGH time
−
5
RFDO setup time to RFCLK HIGH
−
6
RFDO hold time after RFCLK LOW
−
7⁽⁷⁾
RFDI setup time to RFCLK LOW
70
8
RFE setup time to RFEN1 to RFEN4 LOW
−
Baseband Interface timing (DSP Core X_Port) (see Fig.34)
1
SIXEN setup to SIXCLK HIGH
5
2
SIXD setup to SIXCLK HIGH
5
3
SIXD hold time after SIXCLK HIGH
10
4
SIXEN hold time after SIXCLK HIGH
10
5
SIXCLK frequency
−
6
SIXCLK LOW time
20
7
SIXCLK HIGH time
20
8
SOXEN setup time to SOXCLK LOW
20
10
SOXD hold time after SOXCLK LOW
−
11
SOXEN hold time after SOXCLK LOW
10
12
SOXD 3-state after SOXEN HIGH
−
13
SOXCLK frequency
−
14
SOXCLK LOW time
20
15
SOXCLK HIGH time
20
IOM -2 Interface timing (see Figs 35 and 36)
1⁽⁷⁾
DD hold time after DCL HIGH
−30
2a⁽¹³⁾
DCL cycle time
−
2b⁽¹³⁾
DCL cycle time
−
2c⁽¹³⁾
DCL frequency
−
3⁽⁷⁾
FSC hold time after DCL HIGH
−30
4⁽⁷⁾
DU setup time to DCL LOW
50
5⁽⁷⁾
DU hold time after DCL LOW
50
6^(13)(7)
DCL HIGH time
75
7^(13)(7)
DCL LOW time
75
TYP.
4t₁₃
14t₁₃
6t₁₃
6t₁₃
4t₁₃
2t₁₃
−
6t₁₃
−
−
−
−
13
−
−
−
−
−
−
0.27
1800
1800
−
8.5t₁₃
8t₁₃
4.096
−
−
−
−
−
MAX. UNIT
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
MHz
−
ns
−
ns
−
ns
40
ns
−
ns
20
ns
13
MHz
−
ns
−
ns
30
ns
−
ns
−
ns
−
MHz
30
ns
−
ns
−
ns
−
ns
−
ns
1996 Oct 29
119