PCF5083 Datasheet, PDF (10/136 Pages) NXP Semiconductors – GSM signal processing IC

Philips Semiconductors
GSM signal processing IC
Objective specification
PCF5083
SYMBOL
V_SS1
V_DD1
HD4 to HD7
HR/W
HCEN_D
DTACK
SIXCLK
SIXEN
SIXD
SOXCLK
V_DD2
V_SS2
SOXEN
SOXD
CLK20M
FRAME_INT
COMB_INT
HIPR_INT
CLK13M
V_SS1
V_DD1
AFS
ACLK
ADI
ADO
TSCK1
TSCK2
PIN
I/O
99
100
101 to 104 I/O
105
I
106
I
107
O
108
I
109
I
110
I
111
I
112
113
114
I
115
O
116
O
117
O
118
O
119
O
120
O
121
122
123
I/O
124
I/O
125
I
126
O
127
I
128
I
DESCRIPTION
Ground I/O pin.
Supply I/O pin.
Host Interface data (3-state).
Host Interface Write Enable.
Host Interface Enable - DSP core (active LOW).
Host port acknowledge - used as DTACK from DSP core (active LOW, open-drain
output).
DSP serial input port X clock (CMOS level Schmitt trigger input).
DSP serial input port X enable.
DSP serial input port X data.
DSP serial output port X clock (CMOS level Schmitt trigger input).
Supply core.
Ground core.
DSP serial output port X enable.
DSP serial output port X data (3-state).
19.5 MHz CMOS level output.
TDMA frame interrupt (active LOW, open drain output).
Combined interrupt (active LOW, open drain output).
High Priority Interrupt (active LOW, open drain output).
13 MHz CMOS level output.
Ground I/O pin.
Supply I/O pin.
Audio Interface frame sync signal (3-state).
Audio Interface Clock (3-state).
Audio Interface Data In, RS232 clock if enabled.
Audio Interface Data Out (3-state).
Test Clock 1 - tied to V_SS during normal operation.
Test Clock 2 - tied to V_DD2 during normal operation.
1996 Oct 29
10