PCF5083 Datasheet, PDF (110/136 Pages) NXP Semiconductors – GSM signal processing IC

Philips Semiconductors
GSM signal processing IC
Objective specification
PCF5083
Table 94 Parallel Port Data Register
BIT R/W
SYMBOL
0 to 5 R/W PIO0_DATA to PIO5_DATA
OPERATION
PIO0 to PIO5 input or output data
RST = 0 RSTx = 0⁽¹⁾
0
−
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
Table 95 Parallel Port Data Direction Register
BIT
0
1 to 5
R/W
SYMBOL
R PIO0_DDIR
R/W PIO1_DDIR to PIO5_DDIR
OPERATION
reserved
A logic 1 selects the port as an output.
A logic 0 selects the port as an input.
RST = 0
0
0
RSTx = 0⁽¹⁾
−
−
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
Table 96 System Configuration Register (SYSCON)
BIT R/W
SYMBOL
0
W CLK13M
1
W CLK20M
2
W CLK32K
CLK26M
3
W DSP_CLK0
4
W DSP_CLK1
5
W RS232_CLK
6
R LOCK
OPERATION (if bit is set)
Disable the CLK13M output pin.
Disable the CLK20M output pin.
Disable the CLK32K output pin; PCF5083-2B and
PCF5083-2C only.
Disable the CLK26M output pin; PCF5083-3A only.
These two bits select the DSP core input clock.
Select the external clock for the RS232 interface
When a logic 1, the PLL is out of lock. When a logic 0,
the PLL is in lock.
RST = 0
0
0
0
RSTx = 0⁽¹⁾
−
−
−
0
−
0
−
0
−
0
−
0
−
Note
1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘−’ denotes not affected from reset line.
During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other
registers are undefined and have to be set by the controller.
1996 Oct 29
110