SA7016 Datasheet, PDF (11/18 Pages) NXP Semiconductors – 1.3GHz low voltage fractional-N synthesizer

Philips Semiconductors
1.3GHz low voltage fractional-N synthesizer
Product specification
SA7016
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
Serial bus timing characteristics. See Figure 8.
V_DD = V_DDCP =+3.0V; T_amb = +25°C unless otherwise specified.
SYMBOL
PARAMETER
Serial programming clock; CLK
t_r
Input rise time
t_f
Input fall time
T_cy
Clock period
Enable programming; STROBE
t_START
t_W
t_SU;E
Delay to rising clock edge
Minimum inactive pulse width
Enable set-up time to next clock edge
Register serial input data; DATA
t_SU;DAT
t_HD;DAT
Input data to clock set-up time
Input data to clock hold time
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
MIN.
–
–
100
40
1/f_COMP
20
20
20
TYP.
10
10
–
–
–
–
–
–
MAX.
40
40
–
–
–
–
–
–
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Application information
CLK
t_SU;DAT
T_cy
t_HD;DAT
t_r
t_f
t_SU;E
DATA
ADDRESS
MSB
LSB
STROBE
t_START
Figure 8. Serial Bus Timing Diagram
t_w
SR01417
1999 Nov 04
11