PI7C8154A Datasheet, PDF (96/114 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

Bit
13
15:14
PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Function
Ordering Rules
Control 2
Reserved
Type
R/W
R/W
Description
0: Keep the ordering rule requirements between delay read completion
and posted write transactions
1: Disregard the ordering rule requirements between delay read
completion and posted write transactions
Reset to 0
Reset to 0
14.1.48 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET
80h
Bit
Function
Type Description
15:0
Secondary
Master Timeout
R/W
Secondary timeout occurs after 2¹⁵ PCI clocks.
Reset to 8000h.
14.1.49 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h
Bit
31:16
Function
Primary Master
Timeout
Type
R/W
Description
Primary timeout occurs after 2¹⁵ PCI clocks.
Reset to 8000h.
14.1.50 CAPABILITY ID REGISTER – OFFSET B0h
Bit
Function
Type Description
7:0
Enhanced
Capabilities ID
R/O
Read as 04h to indicate that these are Slot Indentification registers.
14.1.51 NEXT POINTER REGISTER – OFFSET B0h
Bit
Function
15:8
Next Item
Pointer
Type
R/O
Description
Read as E8h. Points to Vital Products Data register.
14.1.52 SLOT NUMBER REGISTER – OFFSET B0h
Bit
20:16
21
23:22
Function
Expansion Slot
Number
First in Chassis
Reserved
Type
R/W
R/W
R/O
Description
Indicates expansion slot number
Reset to 0
First in chassis
Reset to 0
Returns 0 when read. Reset to 0
Page 96 of 114
DEC 2009 REVISION 1.02