PI7C8154A Datasheet, PDF (26/114 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
The target returns a target abort (PI7C8154A discards remaining write data).
The master latency timer expires, and PI7C8154A no longer has the target bus grant
(PI7C8154A starts another transaction to deliver remaining write data).
Section 2.11.3.2 provides detailed information about how PI7C8154A responds to target
termination during posted write transactions.
2.6.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C8154A disconnects Memory Write and Invalidate commands at aligned cache line
boundaries. The cache line size value in the cache line size register gives the number of DWORD
in a cache line.
If the value in the cache line size register does meet the memory write and invalidate conditions,
the PI7C8154A returns a target disconnect to the initiator on a cache line boundary.
2.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write
transactions.
A delayed write transaction guarantees that the actual target response is returned back to the
initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a
single DWORD data transfer.
When a write transaction is first detected on the initiator bus, and PI7C8154A forwards it as a
delayed transaction, PI7C8154A claims the access by asserting DEVSEL# and returns a target retry
to the initiator. During the address phase, PI7C8154A samples the bus command, address, and
address parity one cycle later. After IRDY# is asserted, PI7C8154A also samples the first data
DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction
queue. The transaction is queued only if no other existing delayed transactions have the same
address and command, and if the delayed transaction queue is not full. When the delayed write
transaction moves to the head of the delayed transaction queue and all ordering constraints with
posted data are satisfied. The PI7C8154A initiates the transaction on the target bus. PI7C8154A
transfers the write data to the target. If PI7C8154A receives a target retry in response to the write
transaction on the target bus, it continues to repeat the write transaction until the data transfer is
completed, or until an error condition is encountered.
If PI7C8154A is unable to deliver write data after 2²⁴ (default) or 2³² (maximum) attempts,
PI7C8154A will report a system error. PI7C8154A also asserts P_SERR# if the primary SERR#
enable bit is set in the command register. See Section 5.4 for information on the assertion of
P_SERR#. When the initiator repeats the same write transaction (same command, address, byte
enable bits, and data), and the completed delayed transaction is at the head of the queue, the
PI7C8154A claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to
indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8154A
also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those
bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are
turned off (driven HIGH), the corresponding byte of write data is not compared.
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DEC 2009 REVISION 1.02