PI7C8154A Datasheet, PDF (75/114 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
13.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8154A and the
secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are tri-stated.
S_RESET# is asserted and the secondary reset bit is automatically set. S_RESET# remains
asserted until a configuration write operation clears the secondary reset bit. Within 20 PCI clock
cycles after completion of the configuration write operation, PI7C8154A’s reset bit automatically
clears and PI7C8154A is ready for configuration.
During reset, PI7C8154A is inaccessible.
Page 75 of 114
DEC 2009 REVISION 1.02