PI7C8154A Datasheet, PDF (35/114 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
2.9
64-BIT OPERATION
Both the primary and secondary interfaces of the PI7C8154A support 32-bit operation and 64-bit
operation. This chapter describes how to use the 64-bit operations as well as the conditions that go
along with it.
2.9.1
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154A
64-bit transactions are requested by asserting P_REQ64# on the primary and S_REQ64# on the
secondary during the address phase. REQ64# is asserted and deasserted during the same cycles as
FRAME#. Under certain conditions, PI7C8154A does not use the 64-bit extension when initiating
transactions. In this case, REQ64# is not asserted.
If REQ64# is not asserted, the transaction is initiated as a 32-bit transaction when any of the
following conditions are met:
P_REQ64# was not asserted by the primary during reset (64-bit extension not supported on the
primary) for upstream transactions only
PI7C8154A is initiating an I/O transaction
PI7C8154A is initiating a special cycle transaction
PI7C8154A is initiating a configuration transaction
PI7C8154A is initiating a nonprefetchable memory read transaction
The address is not QUADWORD aligned
The address is near the top of a cache line
A single DWORD read transaction is being performed
A single or two-DWORD memory write transaction is being performed
PI7C8154A is resuming memory write transaction after a target disconnect, and ACK64# was
not asserted by the target in the previous transaction – does not apply when the previous target
termination was a target retry
2.9.2
64-BIT TRANSACTIONS – ADDRESS PHASE
When a transaction using the primary bus 64-bit extension is a single address cycle, the upper 32-
bits of the address, AD[63:32], are assumed to be 0 and CBE[7:4] are not defined but driven to
valid logic levels during the address phase.
When a transaction using the primary bus 64-bit extension is a dual address cycle, the upper 32-bit
of the address, AD[63:32], contain the upper 32-bits of the address and CBE[7:4] contain memory
bus command during both address phases. A 64-bit target then has the opportunity to decode the
entire 64-bit address and bus command after the first address phase. A 32-bit target needs both
address phases to decode the full address and bus command.
2.9.3
64-BIT TRANSACTIONS – DATA PHASE
PI7C8154A asserts REQ64# to indicate it is initiating a 64-bit transfer during memory write
transactions. During the data phase, PI7C8154A asserts the following:
The low 32 bits of data on AD[31:0]
The low 4 bits on CBE[3:0]
Page 35 of 112
DEC 2009 REVISION 1.02