PI7C8154A Datasheet, PDF (74/114 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
13 RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
13.1
PRIMARY INTERFACE RESET
PI7C8154A has a reset input, P_RESET#. When P_RESET# is asserted, the following events
occur:
PI7C8154A immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-stated.
PI7C8154A performs a chip reset.
Registers that have default values are reset.
PI7C8154A samples P_REQ64# to determine whether the 64-bit extension is enabled on the
primary.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT.
PI7C8154A is not accessible during P_RESET#. After P_RESET# is de-asserted, PI7C8154A
remains inaccessible for 16 PCI clocks before the first configuration transaction can be accepted.
13.2
SECONDARY INTERFACE RESET
The bridge is responsible for driving the secondary bus reset signals, S_RESET#. Bridge asserts
S_RESET# when any of the following conditions are met:
Signal P_RESET# is asserted. Signal S_RESET# remains asserted as long as P_RESET# is
asserted and does not de-assert until P_RESET# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET# remains asserted
until a configuration write operation clears the secondary reset bit.
The chip reset bit in the diagnostic control register is set. S_RESET# remains asserted until a
configuration write operation clears the secondary reset bit. The S_RESET# in asserting and de-
asserting edges can be asynchronous to P_CLK.
When S_RESET# is asserted, all secondary PCI interface control signals, including the secondary
grant outputs, are immediately tri-stated. Signals S_AD[31:0], S_CBE[3:0], S_PAR are driven low
for the duration of S_RESET# assertion. S_REQ64# is asserted LOW to indicate 64-bit extension
support on the secondary. All posted write and delayed transaction data buffers are reset.
Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S_RESET# is asserted by means of the secondary reset bit, PI7C8154A remains accessible
during secondary interface reset and continues to respond to accesses to its configuration space
from the primary interface.
Page 74 of 114
DEC 2009 REVISION 1.02