PE9704 Datasheet, PDF(8/11 Page) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

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PE9704 Datasheet, PDF (8/11 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

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Serial Interface Mode

Serial Interface Mode is selected by setting the

DMODE input âlowâ.

While the E_WR input is âlowâ, serial data (DATA

input), B0 to B19, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B0) first. The

contents from this buffer register are transferred into

the frequency control register on the rising edge of

S_WR according to the timing diagram shown in

Figure 3. This data controls the counters as shown

in Table 7.

While the E_WR input is âhighâ, serial data (DATA

input), B0 to B7, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B0) first. The

PE9704

Advance Information

contents from this buffer register are transferred into

the enhancement register on the falling edge of

E_WR according to the timing diagram shown in

Figure 3. After the falling edge of E_WR, the data

provides control bits as shown in Table 8. These

bits are active when the Enh input is âlowâ.

Direct Interface Mode

Direct Interface Mode is selected by setting the

DMODE input âhighâ. In this mode, the counter values

are set directly at external pins as shown in Table 7

and Figure 2. All frequency control register bits are

addressable except PB (it is not possible to bypass

the Ã·10/11 dual modulus prescaler in Direct Mode).

Table 7. Frequency Register Programming

Interface

Mode

Enh

Serial*

Direct

DMODE

R2 R1

A1 A0

B10 B11 B12 B13 B14 B15 B16 B17 B18 B19

R5 R4 M8 M7

M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

* Data is clocked serially on CLOCK rising edge while E_WR is âlowâ and transferred to frequency register on S_WR rising edge.

LSB (first in)

MSB (last in)

Table 8. Enhancement Register Programming

Interface

Mode

Enh

DMODE

Reserved*

fp output

Power

down

Counter

load

MSEL

output

fc output

Reserved*

Serial** 0

* Program to 0

* Data is clocked serially on CLOCK rising edge while E_WR is âlowâ and transferred to frequency register on S_WR rising edge.

LSB (first in)

MSB (last in)

Page 8 of 12

File No. 70/0083~00B | | UTSi ï CMOS RFIC SOLUTIONS

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