PE9704 Datasheet, PDF (3/11 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

PE9704
Advance Information
Pin No. Pin Name Interface Mode
Type
Description
M₅
17
GND
Direct
Both
Input
M Counter bit5
Ground
CLOCK
Serial
18
M₆
Direct
19
M₇
Direct
20
M₈
Direct
21
A₀
Direct
22
D_MODE
Both
23
V_DD
Both
Input
Input
Input
Input
Input
Input
(Note 1)
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK.
M Counter bit6
M Counter bit7
M Counter bit8 (MSB)
A Counter bit0
Selects direct interface mode (D_MODE=1) or serial interface mode (D_MODE=0)
Same as pin 1
E_WR
Serial
24
A₁
Direct
25
A₂
Direct
26
A₃
Direct
27
F_IN
Both
28
GND
Both
Input
Input
Input
Input
Input
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A Counter bit1.
A Counter bit2
A Counter bit3 (MSB)
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
Ground.
29
GND
Both
Ground.
30
N/C
No connect.
31
V_DD
32
D_OUT
33
V_DD
34
N/C
Both
Serial
Both
(Note 1)
Output
(Note 1)
Same as pin 1
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to D_OUT through enhancement register programming.
Same as pin 1
No connect.
35
GND
Both
36
PD_D
Both
37
PD_U
Both
38
V_DD
Both
39
C_EXT
Both
Output
(Note 1)
Output
Ground.
PD_D pulses down when f_p leads f_c.
PD_U pulses down when f_c leads f_p.
Same as pin 1
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series resistor.
Connecting C_EXT to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
40
GND
Both
Ground
41
GND
Both
Ground
42
F_R
43
ENH
Both
Both
Input
Output, OD
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
44
LD
Serial
Output
Lock detect output, the open-drain logical inversion of C_EXT. When the loop is locked,
LD is high impedance; otherwise LD is a logic low (“0”).
Note 1: V_DD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
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Copyright  Peregrine Semiconductor Corp. 2003
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