PE9704 Datasheet, PDF(10/11 Page) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

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PE9704 Datasheet, PDF (10/11 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

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Phase Detector Outputs

The phase detector is triggered by rising edges

from the main counter (fp) and the reference counter

(fc). It has two outputs, PD_U, and PD_D. If the

divided VCO leads the divided reference in phase

or frequency (fp leads fc), PD_D pulses âlowâ. If the

divided reference leads the divided VCO in phase

or frequency (fc leads fp), PD_U pulses âlowâ. The

width of either pulse is directly proportional to phase

offset between the two input signals, fp and fc. The

phase detector gain is 430 mV / radian.

PD_U and PD_D are designed to drive an active

loop filter which controls the VCO tune voltage.

PD_U pulses result in an increase in VCO

frequency and PD_D results in a decrease in VCO

frequency.

Software tools for designing the active loop filter

can be found at Peregrineâs web site

(www.peregrine-semi.com).

PE9704

Advance Information

Lock Detect Output

A lock detect signal is provided at pin LD, via the

pin CEXT (see Figure 1). CEXT is the logical âNANDâ

of PD_U and PD_D waveforms, driven through a

series 2k ohm resistor. Connecting CEXT to an

external shunt capacitor provides integration of this

signal.

The CEXT signal is then sent to the LD pin through

an internal inverting comparator with an open drain

output. Thus LD is an âANDâ function of PD_U and

PD_D.

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