PE9704 Datasheet, PDF (2/11 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

Figure 2. Pin Configuration
R₄
R₅
M₀
M₁
V_DD
V_DD
M₂
M₃
S_W R, M₄
DATA, M₅
GND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
C_EXT
V_DD
PD_U
PD_D
GND
N/C
V_DD
D_OUT
V_DD
N/C
GND
PE9704
Advance Information
Table 1. Pin Descriptions
Pin No. Pin Name Interface Mode
Type
1
V_DD
Both
2
R₀
3
R₁
4
R₂
5
R₃
6
GND
7
R₄
8
R₅
9
M₀
10
M₁
11
V_DD
12
V_DD
13
M₂
14
M₃
Direct
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
S_WR
Serial
15
M₄
Direct
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Input
16
DATA
Serial
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-
bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 12
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