PE9704 Datasheet, PDF (6/11 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

PE9704
Advance Information
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Control Interface and Latches (see Figures 1and 3)
f_Clk
CLOCK Serial data clock frequency
t_ClkH
CLOCK Serial clock HIGH time
t_ClkL
CLOCK Serial clock LOW time
t_DSU
DATA set-up time after CLOCK rising edge
t_DHLD
DATA hold time after CLOCK rising edge
t_PW
S_WR pulse width
t_CWR
CLOCK rising edge to S_WR rising edge.
t_CE
CLOCK falling edge to E_WR transition
t_WRC
S_WR falling edge to CLOCK rising edge.
t_EC
E_WR transition to CLOCK rising edge
t_MDO
MSEL data out delay after F_IN rising edge
Main Divider (Including Prescaler)
F_IN
Operating frequency
P_Fin
Input level range
Main Divider (Prescaler Bypassed)
F_IN
Operating frequency
P_Fin
Input level range
Reference Divider
F_R
Operating frequency
P_Fr
Reference input power (Note 2)
Phase Detector
f_c
Comparison frequency
Conditions
(Note 1)
C_L = 12 pf
External AC coupling
External AC coupling
(Note 3)
Single-ended input
(Note 3)
Min
Max
Units
10
MHz
30
ns
30
ns
10
ns
10
ns
30
ns
30
ns
30
ns
30
ns
30
ns
8
ns
500
3000
MHz
-5
5
dBm
50
300
MHz
-5
5
dBm
100
MHz
-2
dBm
20
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V_p-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Copyright  Peregrine Semiconductor Corp. 2003
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