PE9601 Datasheet, PDF (8/14 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications

Functional Description
The PE9601 consists of a prescaler, counters, a
phase detector, a charge pump and control logic.
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and “M”
divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in the
modulus select logic. The phase-frequency
PE9601
Product Specification
detector generates up and down frequency control
signals, which are implemented as a pulse width
modulated current by the charge pump. The
control logic includes a selectable chip interface.
Data can be written via serial bus, parallel bus, or
hardwired direct to the pins. There are also
various operational and test modes and lock
detect.
Figure 5. Functional Block Diagram
f_r
R Counter
f_c
(6-bit)
D(7:0)
Sdata
Control
Pins
Control
Logic
R(5:0)
M(8:0)
A(3:0)
Modulus
Select
F_in
10/11
M Counter
F_in
Prescaler
(9-bit)
Phase
Detector
PD_U
PD_D
Charge
Pump
2k
C
LD
Cext
f_p
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 14
Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions