PE9601 Datasheet, PDF (3/14 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications

PE9601
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode Type
S_WR
Serial
13
D₄
M₄
Parallel
Direct
Sdata
Serial
14
D₅
M₅
Parallel
Direct
Sclk
Serial
15
D₆
M₆
Parallel
Direct
FSELS
Serial
16
D₇
Parallel
Pre_en
Direct
17
GND
ALL
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
FSELP
Parallel
18
A₀
Direct
Serial
E_WR
19
Parallel
Input
Input
Input
Input
A₁
Direct
Input
M2_WR
Parallel
20
A₂
Direct
Input
Input
Smode
Serial, Parallel
Input
21
A₃
Direct
Input
22
Bmode
ALL
Input
23
V_DD
ALL
(Note 1)
24
M1_WR
Parallel
Input
25
A_WR
Parallel
Input
26
Hop_WR
Serial, Parallel
Input
27
F_in
ALL
28
F_in
ALL
29
GND
ALL
Input
Input
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0)
for programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F_in bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0)
for programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on
the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising
edge of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO. Input voltage = 223 mV RMS for guaranteed
operation.
Prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane.
Ground.
Document No. 70-0025-05 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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