PE9601 Datasheet, PDF (7/14 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications

PE9601
Product Specification
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Test Program Name
Conditions
Min
Control Interface and Latches (see Figure 5 and Figure 6)
f_Clk
Serial data clock frequency
(Note 1)
t_ClkH
Serial clock HIGH time
t_clk_H (s)
30
t_ClkL
Serial clock LOW time
t_clk_L (s)
30
t_DSU
Sdata set-up time after Sclk rising t_dsu_”xxx” (s) where
10
edge, D[7:0] set-up time to
“xxx” is name of pin being
M1_WR, M2_WR, A_WR, E_WR tested
rising edge
t_DHLD
Sdata hold time after Sclk rising
t_dhid_”xxx” (s) where
10
edge, D[7:0] hold time to M1_WR, “xxx” is name of pin being
M2_WR, A_WR rising edge
tested
t_PW
S_WR, M1_WR, M2_WR, A_WR, t_pw_”xxx” (s) where “xxx”
30
E_WR pulse width
is name of pin being
tested
t_CWR
Sclk rising edge to S_WR rising
t_cwr_”xxx” (s) where
30
edge. S_WR, M1_WR, M2_WR, “xxx” is name of pin being
A_WR falling edge to Hop_WR
tested
rising edge
t_CE
Sclk falling edge to E_WR
t_ce (s)
30
transition
t_WRC
S_WR falling edge to Sclk rising
t_wrc_”xxx” (s) where
30
edge. Hop_WR falling edge to
“xxx” is name of pin being
S_WR, M1_WR, M2_WR, A_WR tested
rising edge
t_EC
E_WR transition to Sclk rising
t_ec (s)
30
edge
Main Divider (Including Prescaler)
F_in
Operating frequency
P_Fin
Input level range
Main Divider (Prescaler Bypassed)
F_in
Operating frequency
P_Fin
Input level range
Reference Divider
f_r
Operating frequency
P_fr
Reference input power (Note 2)
Phase Detector
f_c
Comparison frequency
RF_sens
RF_sens
Fc_sens
Fc_sens
200
External AC coupling
0
20
External AC coupling
-5
(Note 3)
Single ended input
-2
(Note 3)
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
2200
5
220
5
100
20
ns
MHz
dBm
MHz
dBm
MHz
dBm
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V_p-p.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0025-05 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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