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| PE3339 Datasheet, PDF (8/12 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications | |||
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PE3339
Advance Information
Table 7. Primary Register Programming
Interface Mode Enh
R5
R4
M8
M7 Pre_en M6 M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
B0
B1
B2
B3
B4
B5 B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.
MSB (first in)
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Reserved
Reserved
fp Output
Power
down
Counter
load
MSEL
output
fc output
Serial*
0
B0
B1
B2
B3
B4
B5
B6
*Serial data clocked serially on Sclk rising edge while E_WR âhighâ and captured in the double buffer on E_WR falling edge.
(last in) LSB
Reserved
B7
MSB (first in)
(last in) LSB
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
Copyright © Peregrine Semiconductor Corp. 2004
Page 8 of 12
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
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