PE3339 Datasheet, PDF (2/12 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

Figure 2. Pin Configuration
V_DD ¹
Enh ²
S_WR ³
Sdata ⁴
Sclk ⁵
GND ⁶
FSELS ⁷
E_WR ⁸
V_DD ⁹
F_in ¹⁰
20 _fr
19 _GND
18 _N/C
17 _CP
16 _VDD
15 _Dout
14 _LD
13 _Cext
12 _GND
11 _Fin
PE3339
Advance Information
Table 1. Pin Descriptions
Pin No. Pin Name Type
1
V_DD
(Note 1)
2
Enh
Input
3
S_WR
Input
4
Sdata
Input
5
Sclk
Input
6
GND
7
FSELS
Input
8
E_WR
Input
9
V_DD
10
F_in
(Note 1)
Input
11
F_in
Input
12
GND
13
Cext
Output
14
LD
Output,
OD
15
Dout
Output
16
V_DD
(Note 1)
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up
resistor.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
Ground.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 kΩ pull-down resistor.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.
Same as pin 1.
Prescaler input from the VCO. Max frequency input is 3.0 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 Ω resistor to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
Copyright © Peregrine Semiconductor Corp. 2004
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
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