PE3339 Datasheet, PDF (5/12 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Low Phase Noise Applications

PE3339
Advance Information
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Control Interface and Latches (see Figures 3, 4, 5)
f_Clk
Serial data clock frequency
(Note 1)
t_ClkH
Serial clock HIGH time
t_ClkL
Serial clock LOW time
t_DSU
Sdata set-up time to Sclk rising edge
t_DHLD
Sdata hold time after Sclk rising edge
t_PW
S_WR pulse width
t_CWR
Sclk rising edge to S_WR rising edge
t_CE
Sclk falling edge to E_WR transition
t_WRC
S_WR falling edge to Sclk rising edge
t_EC
E_WR transition to Sclk rising edge
Main Divider (Including Prescaler)
F_in
Operating frequency
P_Fin
Input level range
External AC coupling
Main Divider (Prescaler Bypassed)
F_in
Operating frequency
P_Fin
Input level range
External AC coupling
Reference Divider
f_r
Operating frequency
(Note 3)
P_fr
Reference input power (Note 2)
Single ended input
Phase Detector
f_c
Comparison frequency
(Note 3)
SSB Phase Noise (F_in = 1.3 GHz, f_r = 10 MHz, f_c = 1.25 MHz, LBW = 70 kHz, V_DD = 3.0 V, Temp = -40° C)
100 Hz Offset
1 kHz Offset
Min
Max
Units
10
MHz
30
ns
30
ns
10
ns
10
ns
30
ns
30
ns
30
ns
30
ns
30
ns
500
3000
MHz
-5
5
dBm
50
300
MHz
-5
5
dBm
100
MHz
-2
dBm
20
MHz
-75
dBc/Hz
-85
dBc/Hz
Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3: Parameter is guaranteed through characterization only and is not tested.
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