MN101LR05D Datasheet, PDF (14/34 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.4.2 Pin Description
Table:1.4.1 Power Supply/Oscillation/Reset/Mode Pin
Pin name
MN101LR MN101LR
05D/04D/03D
02D
VDD30
VSS
VDD18
VDD11
VLC1
-
VLC2
VLC3
C1
-
C2
VREFP
OSC1
-
OSC2
XI
XO
NRST
DMOD
NATRON
Input/
Output
Description
- Power supply pin
Connect the capacitor of 1 F or more between VDD30 and VSS.
Apply 0 V to VSS.
- Internal power output pin
Connect the capacitor of 1 F between VDD18 and VSS to stable V_DD18.
Connect the bypass capacitor of 0.1 F between VDD18 and VSS.
- Internal power output pin (1.1 V)
Connect the capacitor of 1 F or more between VDD11 and VSS.
- LCD power supply pin
Supply the power under the following conditions.
(V_DD30  V_LC1  3.6 V and 0 V  V_LC3  V_LC2  V_LC1)
Capacitors described in [17.3.4 LCD Drive Voltage Selection] must be connected in each pin.
When LCD function is not used, connect V_LC1 to V_DD30.
- LCD voltage boost capacitor pin
When using the internal LCD booster circuit, connect the capacitor of 0.22 F between C1 and
C2.
- ADC Reference power supply pin
When ADC is not used, connect VREFP to VDD30.
The voltage level of VREFP must be over 0.8 V_DD30 at any time including LSI power on.
Input External high-speed oscillation pin
Output When the external high-speed oscillation is needed, connect the oscillator to the pins.
The external clock can be input through OSC1, and leave OSC2 open.
Input External low-speed oscillation pin
Output When the external low-speed oscillation is needed, connect the oscillator to the pins.
Input Reset pin (N-channel open drain pin)
Output When NRST is set to "Low", LSI is initialized. LSI reset condition is described in [2.5 Reset].
Input
Mode setting pin
Always set DMOD to "Low" level, except for connecting the external LSI debugger or serial pro-
grammer.
Input
Auto reset control pin
To use the auto reset function, set NATRON to "Low" level.
If not, set NATRON to "High" level.
The voltage level of VREFP must be over 0.8 V_DD30 at any time including LSI power on.
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Publication date: October 2014