MN101EF93G Datasheet, PDF (11/30 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

1.3.3 Pin Functions
MN101EF93G
8-bit Single-chip Microcontroller
PubNo. 21693-013E
Pins
VDD5
VSS
VDD18
OSC1
OSC2
NRST
ATRST
P00
P01
P02
P03
P04
P05
P06
P10
P20
P21
P22
P23
P24
P25
P26
P27
P33
P34
P35
P43
P44
P45
P46
P47
NO
I/O
Function
Description
18
-
Power connect pins
15
-
Apply 4.0 V to 5.5 V to VDD5 and 0 V connect 0.1 F + 1 F or
larger bypass capacitor for internal power stabilization.
19
-
Internal power output pin
This pin is output 1.8 V from internal power circuit. Don’t use the
power supply to external device. For internal power circuit output
stability, connect at least 0.1 F + 1 F one bypass capacitor
between VDD18 and VSS.
16
Input High speed operation clock input pin
Connect these oscillation pins to ceramic or crystal ocsillators for
high-frequency clock operation. If the clock is an external input,
17
Output High speed operation clock output pin
connect it to OSC1 and leave OSC2 open. The chip will not oper-
ate with an external clock when using STOP mode.
12
I/O Reset pin [Active low]
This pin resets the chip when power is turned on, is allocated as
P27 and contains an internal pull-up resistor (Typ. 50 k). Setting
this pin low initialize the internal state of the device. Thereafter,
setting the input to high releases the reset. The hardware waits for
the system clock to stabilize, then processes the reset interrupt. If
a capacitor is to be inserted between NRST and VSS, it is recom-
mended that a discharge diode be placed between NRST and
VDD5.
11
input Auto reset setting pin
Input "High" to enable auto reset function and "Low” to disable this
function
21
22
23
24
I/O I/O port 0
25
7-bit CMOS tri-state I/O port. Each bit can be set individually as
either an input or output by P0DIR register. A pull-up resistor for
each bit can be selected individually by P0PLU register. At reset,
the input mode is selected and pull-up resistor is disabled (high
impedance).
26
27
33
I/O I/O port 1
1-bit CMOS tri-state I/O port. It can be set as either an input or out-
put by P1DIR register. A pull-up resistor can be selected by P1PLU
register. At reset, the input mode is selected and pull-up resistor is
disabled (high impedance).
28
29
30
31
I/O I/O port 2
32
7-bit CMOS tri-state I/O port. Each bit can be set individually as
either an input or output by P2DIR register. A pull-up resistor for
each bit can be selected individually by P2PLU register. At reset,
the input mode is selected and pull-up resistor is disabled (high
impedance)
16
17
12
input input port 2
P27 has an N-channel open-drain configuration.
34
35
I/O I/O port 3
36
3-bit CMOS tri-state I/O port. Each bit can be set individually as
either an input or output by P3DIR register. A pull-up resistor for
each bit can be selected individually by P3PLU register.
At reset, the input mode is selected and pull-up resistor is disabled
(high impedance).
37
38
39
I/O I/O port 4
40
5-bit CMOS tri-state I/O port. Each bit can be set individually as
either an input or output by P4DIR register. A pull-up resistor for
each bit can be selected individually by P4PLU register. At reset,
the input mode is selected and pull-up resistor is disabled (high
impedance).
41
Publication date: February 2015