AND8112 Datasheet, PDF (9/12 Pages) ON Semiconductor – A Quasi-Resonant SPICE Model Eases Feedback Loop Designs

AND8112/D
Putting the Model to Work
Different ways exist to test the validity of a model. The
first one is by using SPICE only, where one can compare the
transient response of the averaged model versus that of the
equivalent cycle−by−cycle. The other one implies the
comparison of the averaged model results versus a real board
measurement. In this paper, we will depict both approaches,
using our simplified cycle−by−cycle transient model.
The averaged template is depicted by Figure 11 where
Figure 10 sources have been pushed into a single graphic
symbol. The symbol must be fed by Lp, Efficiency, R_sense,
transformer turn ratio and the primary inductance ohmic
loss. The FB pin goes to a component arrangement particular
to the NCP1207 series from ON Semiconductor where the
optocoupler collector is internally pulled−up to a reference
voltage.
0.868 8.68 m 80.7
i_P
t_on
f_SW
V_in
120
9
V_g
120
AC =
X2
QuasiFly
L_P = 1.2 m
R_S = 0.5
N = 0.06
eff = 0.91
Rlf = 0.5
I_P t_on f_SW (kHz)
Flyback FreeRunning
L3
R6 ^Vout
V_out
Averaged model
IN
OUT
2.2 m ₂₄10 m
16.8 ₃
16.8
16.8
FB
FB
GND
R8
60 m
17
16.8 _C3
R7
150 m
25
16.8 _C4
R_load
8.5
1 mF
220 m
I_C = 16
I_C =
FB
V9
4.8
R10
20 k
6
4.80
Fb
1.30
C5
1n
V_out
R1
1k
16.7 ₁
X1
SFH615AGR
15.8
2
D4
BV = 15.6
Figure 11. Averaged Model Template
The averaged model template featuring DC bias points which confirms the correct bias point calculation
In Figure 11, once the simulation has been done, DC
points are reflected to the schematic and confirm the validity
of the original calculation. The feedback loop is made of a
simple Zener diode to avoid any long feedback time
constants as with a standard TL431. The cycle−by−cycle
circuitry uses our simplified QR transient model which
emulates a free−running controller such as
ON Semiconductor NCP1207 or NCP1205 [3] (Figure 12).
The output stage and feedback configuration conforms to
Figure 11 in order to compare similar topologies. The first
test consists in testing the input audio susceptibility by
stepping the input voltage from 200 V to 350 VDC.
Figure 13 reveals the good agreement between the averaged
response and the cycle−by−cycle one. The next experience
will step load the converter output from light to heavy load
in a few ms. Figure 14 testifies for the right behavior on both
configuration, average or cycle−by−cycle.
On the static point of view, the following data compare
numbers given by the averaged model and the
cycle−by−cycle one:
I_P AVG = 868 mA / I_P TRAN = 858 mA
T_on AVG = 8.68 ms / T_on TRAN = 8.78 ms
F_SW AVG = 80.7 kHz / F_SW AVG = 77.8 kHz
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