AND8112 Datasheet, PDF (11/12 Pages) ON Semiconductor – A Quasi-Resonant SPICE Model Eases Feedback Loop Designs

AND8112/D
The bandwidth measurement has been carried on a board further to a 15 mn warm−up. This board does not use any clamping
network but a 800 V MOSFET instead and a large capacitor connected between drain and ground Figure 16 and 17 compare
the obtained results with the averaged model including valley and turn−off delays:
Mag (dB)
20
10
0
−10
F0 dB = 49 Hz
−20
High Line
Low Line
−30
−40
−50
−60
1
High Line
Low Line
10
100
1k
10 k
Figure 16. Bode Plot Captured with a Network Analyzer
Phase (°)
180
135
90
45
0
−45
−90
−135
−180
20.0 180
0 90.0
F0 dB = 46 Hz
−20.0 0
Open−loop Gain:
High Line
Low Line
−40.0 −90.0
−60.0 −180
Open−loop Phase:
High Line
Low Line
1
10
100
1k
10 k
100 k
Figure 17. Bode Plot Obtained with the Averaged Model
One can detect a slight gain difference (around 3.5 dB) in
DC but the overall simulated shape stays in good agreement
with the real measurement. The phase dips are imputed to
the presence of the LC network whose cut−off frequency
obviously affects the results. The small−signal analysis
details are available in [5].
Finally, a step−load response was performed on a real
board fed back by a TL−431 network and compared to our
SPICE model, also implementing the same control loop
structure. Results prove that the proposed model accuracy is
acceptable to predict board stability and final transient
response:
http://onsemi.com
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