AND8112 Datasheet, PDF (5/12 Pages) ON Semiconductor – A Quasi-Resonant SPICE Model Eases Feedback Loop Designs

AND8112/D
1
8
2
7
V_{g 3}
6
4
5
NCP1207
D1
V
+
C_out
C_tot ^<=>
V_g
C_tot
Figure 8.
When the power switch turns off, the primary inductor behaves like a current source that charges the C_tot capacitor. This sequence ends
when voltage developed across C_tot exceeds [V_g+(V+V_f)/N], that is when the secondary diode D1 starts to conduct.
2. At the end of the core reset, both switches (power
switch and secondary diode) are off. The primary
inductor L_P together with C_tot form a LC network.
C_tot voltage (and thus the drain source voltage of
the power switch) oscillates around the input
voltage V_g between a peak value (the initial level:
Vg
)
V
N
) and a valley value
Vg
*
V
N
,
the damping
effects being neglected. To benefit from the quasi−
resonant mode, it is recommended to turn the power
switch on in the valley, where the drain−source
voltage is minimized. This naturally reduces the
dV/dt and switching losses to a minimum (in
practice, an appropriate delay inserted after the core
reset detection provides an effective method to
synchronize the power switch turn on with the valley
event). A simple look at Figure 7 shows that the
valley occurs at half the oscillation period.
Therefore, the delay D_t2 between the core reset
completion and the optimal turn on time is given by
the following equation:
D_t2 + p ^ǸLP Ctot
(eq. 25)
Once these delays are defined, it is about time to revise the
previous equations in order to include D_t1 and D_t2 effects.
The main parameters of interest are the average input and
output currents, the equivalent resistance and the switching
period. If we combine equations 24 and 13 that express I_P as
a function of the input voltage, the inductor value and the
ON−time leads to:
D_t1 + LP
Ctot
Vg
)
V
N
Vg ton
(eq. 26)
If (d′ x T_S) depicts the core reset time, D_t1 and D_t2 times
require to change (d′=1−d) into:
dȀ
+
1
*
d
*
D_t1 )
TS
D_t2
(eq. 27)
The inductor volt−second balance approximation of
equation 8 still holds. However, it must be revised by
replacing d′(t) by its novel value as expressed by
equation (27):
t V(LP) u+ d
ǒ Ǔ _{Vg *}
1
*
d
*
D_t1)D_t2
TS
N
V ^{(eq. 28)}
+0
Re−arranging equation (28), one can unveil the duty cycle
expression:
d
+
ǒ_{1 *}
(N
D_t1)D_t2
TS
Vg) )
V^Ǔ
V
(eq. 29)
The switching period is the sum of the on−time, the core
reset time (t_demag), D_t1 and D_t2:
TS + ton ) tdemag ) D_t1 ) D_t2 (eq. 30)
The time t_demag can be easily deducted from the Figure 4
sketch. Since the core reset is the time necessary to discharge
the primary inductor from I_P to zero with a (V+V_f)/N slope,
it comes:
tdemag
+
LP IP
VńN
+
ton
N
Vg
V
(eq. 31)
Substitution of equation (31) into (eq. 30), leads to the
following expression where T_S is a function of t_on:
[(N
TS + D_t1 ) D_t2 )
Vg) ) V]
N
ton
(eq. 32)
Equation (15) that defines the average input current as a
function of the input voltage, the duty cycle, the inductor
value and the switching period, still holds. Substitution of
equation (29) into equation (15) leads to:
t
I1(t)
u+
Vg
2
ǒ Ǔ ₁
*
D_t1)D_t2
TS
V ton
LP [(N Vg) ) V]
(eq. 33)
Replacing T_S by its equation 32 expression, it comes:
Vg
t I1(t) u+
ǒ Ǔ 1
*
D_t1)D_t2
ƪ_(N
D_t1)D_t2)
Vg))V^Æ«
V
ton
2 LP [(N Vg) ) V]
(eq. 34)
V ton
Re−arranging this equation, one can obtain:
http://onsemi.com
5