AND8112 Datasheet, PDF (4/12 Pages) ON Semiconductor – A Quasi-Resonant SPICE Model Eases Feedback Loop Designs

AND8112/D
Re(d)
+
t V1(t) u
t I1(t) u
+
2
d(t)²
LP
TS
(eq. 19)
where the input impedance depends on the duty−cycle d_(t).
However, in quasi−resonant converters, the power transfer
adjusts by varying the peak current I_P which finally imposes
the operating frequency. Since by definition t_on = d x T_S, we
can re−arrange equation 9 to reveal
TS + ton
(N
Vg) ) V
V
(eq. 20)
By finally plugging equation 10 and 20 into 19, we obtain
a t_on−dependent input effective resistance definition:
2
Re(ton) +
LP (V ) N
ton V
Vg)
(eq. 21)
that Figure 5 portrays:
<I_1(t)>
Our switch network can thus modeled according to the
so−called loss−free network where all the power developed
across an input resistance transfers to the output without any
loss (Figure 6) [1].
A More Complex Model Including Parasitic Effects
The above simplified model assumes that there are no
transient times between the conduction and
demagnetization phases. A more precise modelling
approach requires that the two following delays D_t1 and D_t2
are taken into account, as highlighted by Figure 7 and 8:
Core Is Reset!
<V_1(t)>
Re(t_on)
Figure 5.
The average input waveforms of the switch can be modeled via
the above equivalent network.
<I_1(t)>
<P_(t)>
<I_2(t)>
<V_1(t)>
Re(t_on)
<V_2(t)>
Figure 6.
The two−port loss−free network where all the input power trans-
forms into output power.
As reference [1] details, the apparent power consumed by
R_e, P_in, is entirely transmitted to the output since we assume
a 100% efficiency. Therefore, equation 19 can be re−written
by:
t P(t) u+t V1(t) u t I1(t) u+
t V2(t) u
t
I2(t)
u+
t V1(t) u2
Re(ton)
(eq. 22)
D_t1
D_t2
Figure 7.
The presence of a capacitive node slows−down the V_DS rising
and makes the drain sinusoidally ring at the core reset…
1. At the end of the ON−time, the power switch
opens but the energy transfer to the secondary side
does not start immediately. The primary inductor
current (I_P) that cannot flow through the power
switch, charges the surrounding capacitive
elements (C_tot) until C_tot voltage exceeds
Vg
)
V
N
(eq. 23)
At that moment, the secondary diode starts to
conduct and current feeds the output capacitor. One
can assume that the C_tot charging time (D_t1) is short
enough to consider that the primary inductor current
stays equal to I_P during this interval. Then, D_t1 is the
time necessary to charge the capacitor C_tot with a
current I_P from zero to
Vg
)
V
N
, i.e.: D_t1 + Ctot
Vg
)
V
N
IP
(eq. 24)
http://onsemi.com
4