CAT28C17A Datasheet, PDF (8/12 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL E2PROM

ADDRESS
CAT28C17A
CE
WE
OE
I/O7
D_IN = X
t_OEH
t_OE
t_WC
D_OUT = X
Figure 7. DATA Polling
t_OES
D_OUT = X
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C17A.
1. V_CC sense provides for write protection when V_CC
falls below 3.0 V min.
2. A power on delay mechanism, t_INIT (see AC
characteristics), provides a 5 to 20 ms delay before
a write sequence, after V_CC has reached 3.0 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
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