CAT28C17A Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL E2PROM

CAT28C17A
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.
DATA Polling
DATA polling is provided to indicate the completion of a
byte write cycle. Once a byte write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O₇ (I/O₀–I/O₆ are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed byte write cycle, all I/O’s
will output true data during a read cycle.
t_WC
ADDRESS
t_AS
CE
t_AH
t_CW
t_DL
t_OEH
OE
t_OES
t_CS
t_CH
WE
RDY/BUSY
DATA OUT
t_DB
HIGH−Z
DATA IN
DATA VALID
t_DS
t_DH
Figure 6. Byte Write Cycle [CE Controlled]
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