CAT28C17A Datasheet, PDF (5/12 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL E2PROM

CAT28C17A
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform (Note 10)
10. Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
DEVICE
UNDER
TEST
3.3 K
C_L = 100 pF
OUT
C_L INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V_CC = 5 V ±10%, unless otherwise specified.)
28C17A−20
Symbol
Parameter
Min
Max
t_WC
Write Cycle Time
10
t_AS
Address Setup Time
10
t_AH
Address Hold Time
100
t_CS
CE Setup Time
0
t_CH
CE Hold Time
0
t_CW (Note 11) CE Pulse Time
150
t_OES
OE Setup Time
15
t_OEH
OE Hold Time
15
t_WP (Note 11) WE Pulse Width
150
t_DS
Data Setup Time
50
t_DH
Data Hold Time
10
t_DL
Data Latch Time
50
t_INIT (Note 12) Write Inhibit Period After Power−up
5
20
t_DB
Time to Device Busy
80
11. A write pulse of less than 20 ns duration will not initiate a write cycle.
12. This parameter is tested initially and after a design or process change that affects the parameter.
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
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