AR0237CS Datasheet, PDF (8/38 Pages) ON Semiconductor – 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Functional Overview
Figure 3:
Typical Configuration: Parallel Pixel Data Interface
Digital Digital
I/O core
power¹ power¹
PLL Analog Analog
power¹ power¹ power¹
VDD_IO VDD
VDD_PLL VAA VAA_PIX
Master clock
(6-48 MHz)
From
Controller
EXTCLK
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
DGND
VDD_IO
VDD
VDD_PLL
VAA
VAA_PIX
Digital
ground
DOUT [11:0]
PIXCLK
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
AGND
To
controller
Analog
ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for
slower two-wire speed.
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output inter-
face is used.
4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Refer to the AR0237 demo headboard schematics for circuit recom-
mendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6-48 MHz.
AR0237CS/D Rev. 4, 6/16 EN
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©Semiconductor Components Industries, LLC, 2016.