AR0237CS Datasheet, PDF (27/38 Pages) ON Semiconductor – 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Electrical Specifications
Table 7:
Two-Wire Serial Bus Characteristics (continued)
f_{EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; TA = 25°C}
Standard Mode
Fast Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
Serial interface input pin capacitance
CIN_SI
-
3.3
-
3.3
pF
SDATA max load capacitance
SDATA pull-up resistor
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
Notes:
1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I²C-compatible.
3. All values referred to V_IHmin = 0.9 VDD and V_ILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum ^tHD;DAT has only to be met if the device does not stretch the LOW period (^tLOW) of
the SCLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement
t_{SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch}
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line ^tr max + ^tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I²C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0237 launches pixel data, FV, and LV with the falling edge of PIXCLK.
The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of
PIXCLK.
See Figure 14 below and Table 8 on page 28 for I/O timing (AC) characteristics.
Figure 14: I/O Timing Diagram
tR
tF
90%
10%
tRP
tFP
90%
10%
EXTCLK
tEXTCLK
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
tPD
tPLH
tPFH
Pxl _0
Pxl _1
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
Pxl _2
Pxl _n
tPFL
tPLL
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
AR0237CS/D Rev. 4, 6/16 EN
27
©Semiconductor Components Industries, LLC, 2016.