AR0237CS Datasheet, PDF (32/38 Pages) ON Semiconductor – 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

AR0237CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Electrical Specifications
Table 15: 1080p30 74 MHz Line Interleaved SLVS
Definition
Digital Operating Current
Analog Operating Current
Pixel Supply Current
PLL Supply Current
SLVS Supply Current
Condition
Symbol Voltage Min
Typ
Max
Unit
Streaming 1080p30
IDD
1.8
50
88
130
mA
Streaming 1080p30
IAA
2.8
20
36
60
mA
Streaming 1080p30
IAA_PIX
2.8
1
4
8
mA
Streaming 1080p30
IDD_PLL
2.8
7
8.5
9.5
mA
Streaming 1080p30 IDD_SLVS
0.4
6
9.5
14
mA
Power
170.8
298
442.6
mW
Note:
Operating currents are measured in mA at the following conditions:
- VAA = VAA_PIX = VDD_PLL =2.8 V
- VDD = VDD_IO= 1.8 V
- VDD_SLVS= 0.4V
- PLL Enabled and PIXCLK = 74.25 MHz
- 4-lane HiSPi mode
- TA= 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time
Table 16: 1080p30 74 MHz Line Interleaved HiVcm
Definition
Digital Operating Current
Analog Operating Current
Pixel Supply Current
PLL Supply Current
SLVS Supply Current
Condition
Symbol Voltage
Min
Typ
Max
Unit
Streaming 1080p30
IDD
1.8
50
88
130
mA
Streaming 1080p30
IAA
2.8
20
36
60
mA
Streaming 1080p30
IAA_PIX
2.8
1
4
8
mA
Streaming 1080p30
IDD_PLL
2.8
7
8.5
9.5
mA
Streaming 1080p30 IDD_SLVS
1.8
12
20
35
mA
Power
190
330.2
500
mW
Note:
Operating currents are measured in mA at the following conditions:
- VAA = VAA_PIX = VDD_PLL = 2.8 V
- VDD= VDD_IO = 1.8 V
- VDD_SLVS = 1.8 V
- PLL Enabled and PIXCLK = 74.25 MHz
- 4-lane HiSPi mode
- TA = 25°C Dark Image, 8x Analog Gain, HCG, 20ms integration time
HiSPi Electrical Specifications
The ON Semiconductor AR0237 sensor supports both SLVS and HiVCM HiSPi modes.
Refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification
v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS
supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specifica-
tion. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The
DLL as implemented on AR0237 is limited in the number of available delay steps and
differs from the HiSPi specification as described in this section.
Table 17:
Channel Skew
Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.4V; Data Rate =480 Mbps; DLL set to 0
Data Lane Skew in Reference to Clock
tCHSKEW1PHY
-150
ps
AR0237CS/D Rev. 4, 6/16 EN
32
©Semiconductor Components Industries, LLC, 2016.