MC34152 Datasheet, PDF (7/12 Pages) ON Semiconductor – HIGH SPEED DUAL MOSFET DRIVERS

MC34152, MC33152, NCV33152
the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 20, 21, and 22 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as V_CC rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold
is 5.3 V, yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
T_J = T_A + P_D (R_qJA)
where: T_J = Junction Temperature
T_A = Ambient Temperature
P_D = Power Dissipation
R_qJA = Thermal Resistance Junction to Ambient
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
P_D = P_Q + P_{C + P}T
where:
P_Q = Quiescent Power Dissipation
P_C = Capacitive Load Power Dissipation
P_T = Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 17. The
device’s quiescent power dissipation is:
P_Q = V_CC (I_CCL [1−D] + I_CCH [D])
where:
I_CCL = Supply Current with Low State Drive
Outputs
I_CCH = Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
P_C = V_CC (V_OH − V_OL) C_L f
where:
V_OH = High State Drive Output Voltage
V_OL = Low State Drive Output Voltage
C_L = Load Capacitance
f = Frequency
When driving a MOSFET, the calculation of capacitive
load power P_C is somewhat complicated by the changing
gate to source capacitance C_GS as the device switches. To
aid in this calculation, power MOSFET manufacturers
provide gate charge information on their data sheets.
Figure 18 shows a curve of gate voltage versus gate charge
for the ON Semiconductor MTM15N50. Note that there are
three distinct slopes to the curve representing different
input capacitance values. To completely switch the
MOSFET ‘on,’ the gate must be brought to 10 V with
respect to the source. The graph shows that a gate charge
Q_g of 110 nC is required when operating the MOSFET with
a drain to source voltage V_DS of 400 V.
16
MTM15B50
I_D = 15 A
T_A = 25°C
12
V_DS = 100 V
V_DS = 400 V
8.0
8.9 nF
4.0
2.0 nF
0
0
40
D Q_g
C_GS = _{D VGS}
80
120
160
Q_g, GATE CHARGE (nC)
Figure 18. Gate−to−Source Voltage
versus Gate charge
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
P_C(MOSFET) = V_CC Q_g f
The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34152 is able to quickly deliver the required gate
charge for fast power efficient MOSFET switching. By
operating the MC34152 at a higher V_CC, additional charge
can be provided to bring the gate above 10 V. This will
reduce the ‘on’ resistance of the MOSFET at the expense
of higher driver dissipation at a given operating frequency.
The transition power dissipation is due to extremely
short simultaneous conduction of internal circuit nodes
when the Drive Outputs change state. The transition power
dissipation per driver is approximately:
P_T ≈ V_CC (1.08 V_CC C_L f − 8 x 10^−4)
P_T must be greater than zero.
Switching time characterization of the MC34152 is
performed with fixed capacitive loads. Figure 14 shows
that for small capacitance loads, the switching speed is
limited by transistor turn−on/off time and the slew rate of
the internal nodes. For large capacitance loads, the
switching speed is limited by the maximum output current
capability of the integrated circuit.
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