CS1112 Datasheet, PDF (7/12 Pages) ON Semiconductor – Quad Power Output Driver

CS1112
APPLICATION INFORMATION
CIRCUIT DESCRIPTION
The CS1112 was developed for use in very noisy and very
harsh environments such as seen in an automobile system.
The device has four low–side switches all controlled
through an 8–bit Serial Peripheral Interface (SPI) port.
Control of the outputs is also OR’d with parallel inputs. This
is a critical feature enhancement over similar devices
because of the ease in which the parallel inputs can be used
to control the outputs in a Pulse Width Modulation (PWM)
mode. Creating a PWM mode using just the serial port input
is not a practical application.
This part uses ON Semiconductor’s POWERSENSE™
process technology. POWERSENSE combines the
robustness of Bipolar with the dense logic capability of
CMOS, and the power capabilities of DMOS.
Power consumption is kept to a minimum using
POWERSENSE in comparison to a bipolar technology. A
bipolar process requires DC bias currents to power–up the
integrated circuit. This is needed in many applications
requiring analog circuitry, but is not needed here. Digital
POWERSENSE logic dissipates power only when
switching because that is when transient gate charging
current flows. POWERSENSE logic requires little space,
and is a good economical solution. The DMOS side of the
process provides a robust user interface to the outside world
on each of the outputs. Peak transient capability of each
output is rated at a maximum of 46 V (typical of an
automotive load dump transient).
The CS1112 uses quasi–vertical DMOS transistors
resulting in an output resistance (R_DS(ON)) at each output of
less than 1.0 Ω @ 13 V and 500 mA @ 25°C.
The part can be put in a sleep mode where the part draws
less than 2.0 µA of bias current from V_PWR. The part enters
this sleep mode when V_DD ≤ 0.5 V. Maximum quiescent
current for the device is 5.0 mA maximum for any
combination of output drivers enabled.
Fault reporting is controlled by the CS1112. Overcurrent
and short to V_BATT are detected when the output is on. Open
load and short to ground are detected when the output is off.
Faults are reported out of the serial output (SO) pin as a new
8–bit word is being fed into the serial input (SI) pin.
Figure 3 highlights the SPI interface between the
microprocessor and the CS1112. The SPI control inputs and
all other logic inputs are compatible with 5.0 V CMOS logic
levels.
Parallel
Inputs
µP
CS1112
SI
Control
IN0
µP
Receive Buffer
SO
SCLK
CSB
Shift Register
XXXX3 2 10
3 210
Output Logic
IN1
IN2
STATUS
SPI Interface
Fault Reporting
Figure 3.
The four communication lines which define the SPI
interface are the SI, SO, CSB, and SCLK. The parallel
inputs, which control the outputs can also connect to the
same microprocessor, a separate microprocessor, or any
other sensor or electrical device which meets the voltage
requirements of the CS1112 (V_IN(max) = V_DD + 0.3 V).
SPI communication is as follows (2 scenarios):
1.
8–Bit Normal Operation
CSB pin is brought low activating the SPI port. Faults
detected since the last CSB low to high transition are
latched into the serial register when CSB goes low. 8
command bits are clocked into the SI pin. The four
fault bits are clocked out of the SO pin. CSB pin is
brought high translating the final 4 bits to the outputs
turning them on or off. Faults are then detected and
saved in the fault register when CSB goes low.
2.
16–Bit Operation For Command Verify
CSB pin is brought low activating the SPI port. 16 bits
are clocked into the SI pin (the last 4 are the 4 control
pins for the four outputs). CSB pin is brought high
translating the last 4 bits to the outputs turning them
on or off.
CSB pin is brought low activating the SPI port. 16
new bits are clocked into the SI pin. As the new bits
are being clocked in, the first 8 bits being clocked out
of the SO pin are the fault bits, followed by the first
8 bits which were clocked in (the verification bits).
The verification bits should replicate the command
bits.
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