CS1112 Datasheet, PDF (4/12 Pages) ON Semiconductor – Quad Power Output Driver

CS1112
ELECTRICAL CHARACTERISTICS (continued) (9.0 V < V_PWR < 17 V, 4.5 V < V_DD < 5.5 V, –40°C < T_{J <} 125°C,
5.5 V < V_PWR < 25 V, (Outputs Functional); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Serial Peripheral Interface
SCLK Clock Period
MAX Input Capacitance
V_PWR = 14 V
C_O = 200 pF
SI, SCLK, Note 1.
250
–
–
–
–
ns
12
pF
V_OUT High
V_OUT Low
SCLK High Time
SO, I_OH = 1.0 mA
V_DD – 1.0
–
SO, I_OL = 1.0 mA
–
–
F_SCLK = 4.0 MHz, SCLK = 2.0 V to 2.0 V
125
–
(see Figure 1)
–
V
0.5
V
–
ns
SCLK Low Time
F_SCLK = 4.0 MHz, SCLK = 0.8 V to 0.8 V
125
–
(see Figure 1)
–
ns
SI Setup Time
SI = 0.8 V/2.0 V to SCLK = 2.0 V at 4.0 MHz;
25
–
Note 1. (see Figure 1)
–
ns
SI Hold Time
SCLK = 2.0 V to SI = 0.8 V/2.0 V at 4.0 MHz;
25
–
Note 1. (see Figure 1)
–
ns
SO Rise Time
C_LD = 200 pF (0.1 V_DD to 0.9 V_DD);
Note 1.
–
25
50
ns
SO Fall Time
C_LD = 200 pF (0.9 V_DD to 0.1 V_DD);
Note 1.
–
–
50
ns
CSB Setup Time
CSB = 0.8 V to SCLK = 2.0 V
(see Figure 1) Note 1.
60
–
–
ns
CSB Hold Time
SCLK = 0.8 V to CSB = 2.0 V
(see Figure 1) Note 1.
75
–
–
ns
SO Delay Time
SCLK = 0.8 V to SO Data Valid, V_DD = 5.0 V
–
C_LD = 200 pF at 4.0 MHz
(see Figure 1); Note 1.
65
125
ns
Xfer Delay Time
CSB rising edge to next falling edge.
Note 1.
1.0
–
–
µs
1. Guaranteed by design.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
24 Lead SOIC
1
2
3
4
5, 6, 7, 8
17, 18, 19, 20
9
10
11
12
13
14
PIN SYMBOL
V_DD
V_PWR
OUT0
IN0
GND
IN1
OUT1
SI
CSB
SCLK
SO
FUNCTION
Input voltage to bias logic and control circuitry.
Input voltage to bias gate drive circuitry.
Open drain output one.
Parallel input one.
Ground Reference.
Parallel input two.
Open drain output two.
SPI serial input.
SPI active low chip select.
SPI clock input.
SPI serial output.
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