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| CM1231-02SO Datasheet, PDF (7/12 Pages) ON Semiconductor – 2,4,8-Channel Low-Capacitance ESD Protection Array | |||
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CM1231â02SO
GRAPHICAL COMPARISON AND TEST SETUP
The following graphs (see Figure 6, Figure 7 and Figure 8) show that the CM1231â02SO (dual stage ESD protector) lowers
the peak voltage and clamping voltage by 40% across a wide range of loading conditions in comparison to a standard single
stage device. This data was derived using the test setups shown in Figure 9 and Figure 10.
Figure 6. IEC 61000â4â2 Vpeak vs. Loading (RDUP*)
Figure 7. IEC 61000â4â2 Vclamp vs. Loading (RDUP*)
*RDUP indicates the amount of Resistance (load) supplied to the Device Under Protection (DUP) through a variable resistor.
Figure 8. IEC 61000â4â2 IRES (Residual ESD Peak Current) vs. Loading (RDUP)
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