CM1231-02SO Datasheet, PDF (11/12 Pages) ON Semiconductor – 2,4,8-Channel Low-Capacitance ESD Protection Array

CM1231−02SO
APPLICATION INFORMATION
CM1231−02SO Application and Guidelines
The CM1231−02SO has an integrated zener diode
between V_P and V_N (for each of the two stages). This greatly
reduces the effect of supply rail inductance L₂ on V_CL by
clamping V_P at the breakdown voltage of the zener diode.
However, for the lowest possible V_CL, especially when V_P
is biased at a voltage significantly below the zener
breakdown voltage, it is recommended that a 0.22 mF
ceramic chip capacitor be connected between V_P and the
ground plane.
With the CM1231−02SO, this additional bypass capacitor
is generally not required.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor
mentioned above should be as close to the V_P pin of the
Protection Array as possible, with minimum PCB trace
lengths to the power supply, ground planes and between the
signal input and the ESD device to minimize stray series
inductance.
Figure 14. Typical Layout with Optional V_P Cap Footprint
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection,” in the Applications section.
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