CM1231-02SO Datasheet, PDF (5/12 Pages) ON Semiconductor – 2,4,8-Channel Low-Capacitance ESD Protection Array

ESD Strike
CM1231−02SO
I/O Connector
1W
ESD
Protection
Stage 1
ESD
Protection
Stage 2
ASIC
I_SHUNT1
I_SHUNT2
I_RESIDUAL
Figure 2. Dual Clamp ESD Protection Block Diagram
CM1231−02SO ARCHITECTURE OVERVIEW
The two−stage per channel matched clamp architecture
with isolated clamp rails features a series element to
radically reduce the residual ESD current (I_RES) that enters
the ASIC under protection (see Figure 3). From stage 1 to
stage 2, the signal lines go through matched dual 1 W
resistors.
The function of the series element (dual 1 W resistors for
the CM1231−02SO) is to optimize the operation of the stage
two diodes to reduce the final I_RES current to a minimum
while maintaining an acceptable insertion impedance that is
negligible for the associated signaling levels.
Each stage consists of a traditional low−cap Dual Rail
Clamp structure which steer the positive or negative ESD
current pulse to either the positive (V_P) or negative (V_N)
supply rail.
A zener diode is embedded between V_P and V_N, offering
two advantages. First, it protects the V_CC rail against ESD
strikes. Second, it eliminates the need for an additional
bypass capacitor to shunt the positive ESD strikes to ground.
The CM1231−02SO therefore replaces as many as seven
discrete components, while taking advantage of precision
internal component matching for improved signal integrity,
which is not otherwise possible with discrete components at
the system level.
V_P
Positive Supply Rail
V_CC
I_ESD
1W
I_RESIDUAL
Circuitry
Under
Protection
V_N
Ground Rail
Figure 3. CM1231−02SO Block Diagram (I_ESD Flow During a Positive Strike)
http://onsemi.com
5