74HC373 Datasheet, PDF (6/9 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

74HC373
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to 25_C v 85_C
v 125_C
V_CC
Figure (V) Min Max Min Max Min Max Unit
t_su Minimum Setup Time, Input D to Latch Enable
4
2.0 25
30
40
ns
3.0 20
25
30
4.5 5.0
6.0
8.0
6.0 5.0
6.0
7.0
t_h
Minimum Hold Time, Latch Enable to Input D
4
2.0 5.0
5.0
5.0
ns
3.0 5.0
5.0
5.0
4.5 5.0
50
5.0
6.0 5.0
5.0
5.0
t_w
Minimum Pulse Width, Latch Enable
2
2.0 60
75
90
ns
3.0 23
27
32
4.5 12
15
18
6.0 10
13
15
t_r, t_f Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000 ns
800
500
400
SWITCHING WAVEFORMS
t_r
INPUT D
t_PLH
Q
90%
50%
10%
90%
50%
10%
t_TLH
t_f
V_CC
t_w
V_CC
LATCH ENABLE
50%
GND
GND
t_PHL
t_PLH
t_PHL
Q
50%
t_THL
Figure 1.
Figure 2.
OUTPUT
ENABLE
50%
V_CC
GND
VALID
t_PZL t_PLZ
Q
50%
HIGH
IMPEDANCE
INPUT D
50%
V_CC
GND
10% _VOL
t_su
t_h
t_PZH t_PHZ
90% ^VOH
LATCH ENABLE
V_CC
50%
Q
1.3 V
HIGH
GND
IMPEDANCE
Figure 3.
Figure 4.
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