74HC373 Datasheet, PDF (5/9 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

74HC373
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
Parameter
V_CC
Guaranteed Limit
(V) – 55 to 25_C v 85_C v 125_C Unit
t_PLH Maximum Propagation Delay, Input D to Q
t_PHL
(Figures 1 and 5)
2.0
125
3.0
80
4.5
25
6.0
21
155
190
ns
110
130
31
38
26
32
t_PLH Maximum Propagation Delay, Latch Enable to Q
t_PHL
(Figures 2 and 5)
2.0
140
3.0
90
4.5
28
6.0
24
175
210
ns
120
140
35
42
30
36
t_PLZ Maximum Propagation Delay, Output Enable to Q
t_PHZ
(Figures 3 and 6)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
t_PZL Maximum Propagation Delay, Output Enable to Q
t_PZH
(Figures 3 and 6)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
t_TLH Maximum Output Transition Time, Any Output
t_THL
(Figures 1 and 5)
2.0
60
3.0
23
4.5
12
6.0
10
75
90
ns
27
32
15
18
13
15
C_in Maximum Input Capacitance
C_out Maximum Three−State Output Capacitance
(Output in High−Impedance State)
10
10
10
pF
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Enabled Output)*
36
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
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