74HC373 Datasheet, PDF (2/9 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

LOGIC DIAGRAM
74HC373
DATA
INPUTS
D0 ³
D1 ⁴
D2 ⁷
D3 ⁸
D4 ¹³
D5 ¹⁴
D6 ¹⁷
D7 ¹⁸
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
2 _Q0
5 _Q1
6 _Q2
9 _Q3
12 _Q4
15 _Q5
16 _Q6
19 _Q7
NONINVERTING
OUTPUTS
PIN 20 = V_CC
PIN 10 = GND
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
46.5
1.5
5.0
0.0075
Units
ea
ns
mW
pJ
PIN ASSIGNMENT
OUTPUT ₁
ENABLE
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V_CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 ^LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L
H
H
L
H
L
L
L
X
H
X
X
X = Don’t Care
Z = High Impedance
H
L
No Change
Z
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