MC74HC4351 Datasheet, PDF (5/13 Pages) ON Semiconductor – High−Performance Silicon−Gate CMOS

MC74HC4351
TIMING REQUIREMENTS (Input t_r = t_f = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _VCC
Symbol
Parameter
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tsu
Minimum Setup Time, Channel−Select to Latch Enable
2.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 12)
4.5
6.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Latch Enable to Channel Select
2.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 12)}
4.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^6.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tw
Minimum Pulse Width, Latch Enable
2.0
(Figure 12)
4.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _6.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tr, tf}
Maximum Input Rise and Fall Times, Channel−Select, Latch Enable, 2.0
and Enables 1 and 2
4.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^6.0
Guaranteed Limit
– 55 to
25_C v 85_C v 125_C _Unit
100
125
150
ns
20
25
30
17
21
26
0
0
0
ns
0
0
0
0
0
0
80
100
120
ns
16
20
24
14
17
20
1000
1000
1000
ns
500
500
500
400
400
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D).
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
Limit*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Test Condition
V_CC
V_EE
V
V
25_C
54/74HC
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{BW Maximum On–Channel Bandwidth or fin = 1 MHz Sine Wave}
51 52 53 ^MHz
Minimum Frequency Response
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 6)}
Adjust f_in Voltage to Obtain 0 dBm at V_OS
Increase f_in Frequency Until dB Meter
Reads – 3 dB
2.25 – 2.25 ^{80 95 120}
4.50 – 4.50 ^{80 95 120}
R_L = 50 Ω, C_L = 10 pF 6.00 – 6.00 ^{80 95 120}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _—
Off–Channel Feedthrough Isolation f_in  Sine Wave
dB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 7)}
Adjust f_in Voltage to Obtain 0 dBm at V_IS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ f_in = 10 kHz, R_L = 600 Ω, C_L = 50 pF 2.25 – 2.25
– 50
4.50 – 4.50
– 50
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{6.00 –6.00}
– 50
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 2.25 – 2.25}
– 40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 4.50 –4.50
– 40
6.00 – 6.00
– 40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _—
Feedthrough Noise, Channel Select V_in v 1 MHz Square Wave
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Input to Common O/I}
(t_r = t_f = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 8)}
Adjust R_L at Setup so that I_S = 0 A
mV_PP
Enable = GND
2.25 – 2.25
25
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{RL = 600 Ω, CL = 50 pF 4.50 – 4.50}
105
6.00 – 6.00
135
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{RL = 10 kΩ, CL = 10 pF 2.25 – 2.25}
35
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{4.50 –4.50}
145
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.00 –6.00
190
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ —
Crosstalk Between Any Two Switches f_in  Sine Wave
dB
(Figure 13)
Adjust f_in Voltage to Obtain 0 dBm at V_IS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Test does not apply to HC4351) fin = 10 kHz, RL = 600 Ω, CL = 50 pF}
2.25 – 2.25
– 50
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 4.50 –4.50
– 50
6.00 – 6.00
– 50
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{fin = 1 MHz, RL = 50 Ω, CL = 10 pF 2.25 – 2.25}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{4.50 –4.50}
– 60
– 60
6.00 – 6.00
– 60
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _THD
Total Harmonic Distortion
(Figure 15)
f_in = 1 kHz, R_L = 10 kΩ, C_L = 50 pF
%
THD = THD_Measured – THD_Source
V_IS = 4.0 V_PP sine wave 2.25 – 2.25
0.10
V_IS = 8.0 V_PP sine wave 4.50 – 4.50
0.08
V_IS = 11.0 V_PP sine wave 6.00 – 6.00
0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{*Limits not tested. Determined by design and verified by qualification.}
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