MC74HC4351 Datasheet, PDF (10/13 Pages) ON Semiconductor – High−Performance Silicon−Gate CMOS

MC74HC4351
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
V_CC or GND logic levels. V_CC being recognized as a logic
high and GND being recognized as a logic low. In this
example:
V_CC = + 5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swings are determined by
the supply voltages V_CC and V_EE. The positive peak analog
voltage should not exceed V_CC. Similarly, the negative peak
analog voltage should not go below V_EE. In this example,
the difference between V_CC and V_EE is ten volts. Therefore,
using the configuration in Figure 16, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to V_CC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies
are that:
V_CC − GND = 2 to 6 volts
V_EE − GND = 0 to − 6 volts
V_CC − V_EE = 2 to 12 volts
and V_EE v GND
When voltage transients above V_CC and/or below V_EE
are anticipated on the analog channels, external
Germanium or Schottky diodes (D_x) are recommended as
shown in Figure 17. These diodes should be able to absorb
the maximum anticipated current surges during clipping.
+5 V
+5V
20
+5V
−5V
ANALOG
SIGNAL
ON
ANALOG
SIGNAL
−5V
+5 V
7
15
TO EXTERNAL CMOS
8
13
CIRCUITRY
9
12
10 11
0 TO 5 V DIGITAL
SIGNALS
−5 V
Figure 16. Application Example
V_CC
V_CC
V_CC
D_x
20
D_x
ON/OFF
D_x
D_x
V_EE
V_EE
9
10
V_EE
Figure 17. External Germanium or
Schottky Clipping Diodes
+5V
+5V
+5V
V_EE
20
+5V
ANALOG
SIGNAL
ON/OFF
ANALOG
SIGNAL
+5V
V_EE
+5V
V_EE
ANALOG
SIGNAL
20
ON/OFF
ANALOG
SIGNAL
+5V
V_EE
*
V_CC
RR R R
7
15
8
13
9
12
10
11
LSTTL/NMOS
CIRCUITRY
V_EE
* 2 k ≤ R ≤ 10 k
a. Using Pull−Up Resistors
V_CC
7
15
8
13
9
12
10
11
+5
LSTTL/NMOS
CIRCUITRY
V_EE
HCT
BUFFER
b. Using HCT Interface
Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs
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