MC74HC4351 Datasheet, PDF (2/13 Pages) ON Semiconductor – High−Performance Silicon−Gate CMOS

MC74HC4351
LOGIC DIAGRAM
MC54/74HC4351
Single−Pole, 8−Position Plus Common Off and Address Latch
ANALOG
INPUTS/OUTPUTS
X0 ¹⁷
X1 ¹⁸
X2 ¹⁹
X3 ¹⁶
X4 ¹
X5 ⁶
X6 ²
X7 ⁵
FUNCTION TABLE
MC54/74HC4351
MULTIPLEXER/
DEMULTIPLEXER
4
COMMON
X _OUTPUT/INPUT
CHANNEL−SELECT
INPUTS
A
B
15
13
CHANNEL
ADDRESS
C ^{12 LATCH}
LATCH ENABLE ¹¹
SWITCH ENABLE 1 ⁷
ENABLES _{ENABLE 2} ⁸
PIN 20 = V_CC
PIN 9 = V_EE
PIN 10 = GND
PINS 3, 14 = NC
Control Inputs
Enable
Select
1 2CBA
ON
Channel
(LE = H)*
L HLLL
L HLLH
L HLHL
L HLHH
L HHL L
L HHLH
L HHHL
L HHHH
H XXXX
X LXXX
X0
X1
X2
X3
X4
X5
X6
X7
None
None
X = don’t care
*When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
BLOCK DIAGRAM
MC54/74HC4353
Triple Single−Pole, Double−Position Plus Common Off and Address Latch
X0 ¹⁶
X1 ¹⁷
X SWITCH
18 _X
PIN ASSIGNMENT
Y1 1
20 V_CC
FUNCTION TABLE
Y0 ²
Y1 ¹
Y SWITCH
19 _Y
COMMON
OUTPUT/INPUT
Y0 2
Control InNpCuts 3
Enable
S_Ze₁ lec₄t
19 Y
18 X
On
17 ChaXn1nel
Z0 ⁶
Z1 ⁴
Z SWITCH
5Z
1
2 C _ZB ₅ A
16^(LEX⁼0 ^H)*
L H L L L Z0 Y0 X0
L H L ^Z0 L ⁶ H Z¹0^{5 A}Y0 X1
CHANNEL−SELECT
INPUTS
A
B
15
13
CHANNEL
ADDRESS
C ^{12 LATCH}
LATCH ENABLE ¹¹
SWITCH ENABLE 1 ⁷
ENABLES _{ENABLE 2} ⁸
PIN 20 = V_CC
PIN 9 = V_EE
PIN 10 = GND
PINS 3, 14 = NC
L
L
H
H
ENA^LLBLE 1^HH
7
L
H
ZZ₁00_{4 N}YY_C11
X0
X1
L H _ENAH_{BLE 2} L ₈ L Z₁1_{3 B}Y0 X0
L H H L H Z1 Y0 X1
L H H V_EEH 9 L Z112 CY1 X0
L
H
H
X
HX _GNDHX
10
H
X
Z₁1₁
L^YA¹TCH ^X1
N_Eo_Nn_Ae_BLE
X LXXX
None
X = Don’t Care ^{NC = NO CONNECTION}
*When Latch Enable is low, the Channel
NOTE:
This device allows independent control of each switch. Channel−Select
Selection is latched and the Channel Address
Latch does not change states.
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.
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