LC823450 Datasheet, PDF (45/55 Pages) ON Semiconductor – Low Power & High-Resolution Audio Processing System LSI

LC823450
Item
Xtal Input
frequency
Symbol
Fxin1
Function
System,
Audio clock
(XT1 oscillator)
Low voltage
operation
Min
Typ
Max
12MHz or 20MHz
tolerance : ±200ppm or less
Jitter : ±50ps or less
High voltage
operation
Unit
Min
Typ
Max
12MHz or 20MHz or
-
24MHz or 48MHz
tolerance : ±200ppm or less
Jitter : ±50ps or less
FxinRTC
Frc
Time for
Xtal stable
Txin1
TxinRTC
Internal
clock
frequency
Farm
Fahb
Fapb
Fdsp
Faud(*1)
Fdec
Fenc
RTC clock
(XTRTC oscillator)
RC
(RC oscillator)
Cortex-M3
AHB
APB
DSP
AUDCLK(768fs)
DECCLK(*2)
(MP3 Decoder)
ENCCLK(*3)
(MP3 Encoder)
(*4)
32.768kHz
Jitter : ±500ps or less
0.4
1
2
(*5)
(*5)
(*5)
3
(*7)
1000
(*7)
0
100
0
100
0
100
0
100
0
33.8688 147.456
0
16.9344 73.728
0
8.4672 36.864
(*4)
same as left
same as left
same as left
-
MHz
ms
same as left
ms
0
160(*6) MHz
0
160(*6) MHz
0
160(*6) MHz
0
160(*6) MHz
same as left
MHz
same as left
MHz
same as left
MHz
(*1) Audio blocks run on 256 * Fs(sampling frequency) clock.
However, Class-D AMP, etc run on 384 * Fs(sampling frequency).
These clocks are generated from 768 * Fs(Base Clock) divided by 3 and 2 respectively.
(*2)MP3 Decoder runs on clock of 384 * Fs(sampling frequency of MPEG1 mode).
It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG2 /
2.5 mode(Fs = 22.05 / 11.025KHz as an example), please supplies 16.9344MHz(= 384 * 44.1KHz) clock which is the same clock
frequency as MPEG1 mode.
(*3) MP3 Encoder runs on clock of 192 * Fs(sampling frequency of MPEG1 mode).
It runs on the clock of the same frequency as MPEG1 mode during MPEG2 / 2.5 mode. For example, even when operating in MPEG2 /
2.5 mode(Fs = 22.05 / 11.025KHz as an example), please supplies 8.4672MHz(= 192 * 44.1KHz) clock which is the same clock
frequency as MPEG1 mode.
(*4) Refer to the detailed datasheet. If USB function is not used, the specification required may be relaxed. Please contact our representative
in detail.
(*5) Vdd1=0.93V to 1.27V, Ta=−20°C to 65°C
(*6) When Farm, Fdsp are over 100MHz, 1 * Wait is required for Cortex-M3 and LPDSP32 to access internal ROM by the register described
in the ProgrammersModel_SystemController as memory access control register4.
(*7) These are just reference values under Ta=25°C, and need to be adjusted to customer board situation.
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