LC823450 Datasheet, PDF (18/55 Pages) ON Semiconductor – Low Power & High-Resolution Audio Processing System LSI

LC823450
(L) Xtal, PLL
Terminal name
Multiplexed function
Polarity Direction Function
IO POWER
Available(○)
TA
XA,
XC
XB,
XD
XIN1
−
I
XTAL input (XT1)
VddXT1
○○○
XOUT1
−
O
XTAL output (XT1)
VddXT1
○○○
VddXT1
−
P
XTAL power supply
(XT1)
−
○○○
VssXT1
−
P
XTAL ground (XT1)
−
○○○
XTALINFO[1:0]
XTAL frequency input
(*1)
XTALINFO[1:0] =
 “00” : 24MHz
 “01” : 12MHz
 “10” : 20MHz
−
B
 “11” : 48MHz
Vdd2
Used for determining
clock frequency
setting while internal
ROM boot.
Bonding internally for
“TA” product
○○
VCNT1
−
O
PLL1 VCO control
AVddPLL1
○○○
AVddPLL1
−
P
PLL1 analog power
supply
−
○○○
AVssPLL1
−
P
PLL1 analog ground
−
○○○
VCNT2
−
O
PLL2 VCO control
AVddPLL2
○
(*2)
○
○
AVddPLL2
−
P
PLL2 analog power
supply
−
○
(*2)
○
○
VCNT3
−
O
PLL3 VCO control
AVddPLL3
○
(*3)
○
○
AVddPLL3
−
P
PLL3 analog power
supply
−
○
(*3)
○
○
AVssPLL2
−
P
PLL2/3 analog
ground(*4)
−
○○○
Sum
(*1) Set according to the frequency of XT1(12/20/24/48MHz).
10 14 14
Bonding internally for “TA” product as described on Page 5.
(*2),(*3) Audio clock is generated by one of PLL2(1V) or PLL3(3V).
One of PLL2 or PLL3 is available for “TA” and “RA” product. Please refer to Page 5 for more information.
Both of PLL2 and PLL3 are available for “XA”, “XB”, “XC” and “XD” products.
(*4) Analog ground is shared by PLL2 and PLL3.
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