LC823450 Datasheet, PDF (2/55 Pages) ON Semiconductor – Low Power & High-Resolution Audio Processing System LSI

LC823450
1 Abstract
1-1 Features
 Cortex-M3 Dual Core, AMBA^® (AHB/APB) system
- Internal SRAM (1.5M-byte)
- Internal ROM (256k-byte). Boot code, Standard Functions
- SDRAM Controller (1 * CS)
64M to 256Mbit SDRAM / Mobile SDRAM
- External Memory Controller (2 * CS)
NOR FLASH, SRAM, ROM supported, 8/16 bit I/F LCD controller supported
Internal ROM boot and External memory device boot available
- DMA Controller (8ch)
- Interrupt Controller (External 90ch, Internal 82ch)
- SPI (1ch)
- Serial Flash I/F (1ch)
Quad SPI, cache memory (16k-byte, 4way set associative, 128line) function available
1.8V dedicated power supply
- UART (3ch)
UART1 : w/flow control (CTS, RTS)
UART0, UART2 : w/o flow control
- I2C (2ch) Single Master, Full/Standard
- GPIO (90 ch)
- Plain Timer w/ Watch Dog Timer (1ch×3)
- Multiple Timer (2ch×4)
- 10bit ADC (6ch)
- SD Card I/F (3ch)
eSD/eMMC, UHS-I, w/o CPRM
 SD0 : eSD/eMMC boot supported (Internal ROM Boot function)
1.8V dedicated power supply
 SD1 : Multiplexed w/ Memory Stick I/F
1.8V dedicated power supply
 SD2 :
1.8V dedicated power supply
- Memory Stick I/F (1ch)
Multiplexed w/ SD1
- USB2.0 Host (HS/FS/LS) Controller, Device (HS/FS) Controller. Integrated PHY
Xtal (XT1) is required for USB function.
48 MHz for Host, and 12,20,24,48 MHz for device
w/o OTG function. Host and Device share an integrated PHY.
- Real Time Clock
2 modes below are available
 General RTC mode : RTC w/o key input
 KeyInt RTC mode : RTC w/ key input which enables power on function
- SWD (Serial Wire Debug) is supported as the debug interface
SWV (Serial Wire Viewer) is supported as the trace interface
Only one of Cortex-M3 Dual Core can be traced.
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